1. Field of the Invention
This invention relates generally to the field of digital interface design and, more particularly, to memory management design in a graphics system.
2. Description of the Related Art
With each new generation of graphics system, there is more image data to process and less time in which to process it. This consistent increase in data and data rates places additional burden on the memory systems that form an integral part of the graphics system. Attempts to further improve graphics system performance are now running up against the limitations of these memory systems in general, and memory device limitations in particular.
One example of a memory sub-system defining the upper limit of overall system performance may be the texture buffer of a graphics system. Certain graphics applications such as 3D modeling, virtual reality viewers, and video games may call for the application of an image to a geometric primitive in lieu of a procedurally generated pattern, gradient or solid color. In these applications, geometric primitives carry additional mapping data (e.g., a UV, or UVQ map), which describes how the non-procedural data is to be applied to the primitive. To implement this type of function, a graphics system may employ a texture buffer to store two dimensional image data representative of texture patterns, “environment” maps, “bump” maps, and other types of non-procedural data.
During the rendering process, the mapping data associated with a primitive may be used to interpolate texture map addresses for each pixel in the primitive. The texture map addresses may then be used to retrieve the portion of non-procedural image data in the texture buffer to be applied to the primitive. In some cases (e.g., photo-realistic rendering) a fetch from the texture buffer may result in a neighborhood or tile of texture pixels or texels to be retrieved from the texture buffer and spatially filtered to produce a single texel. In these cases, four or more texels may be retrieved for each displayed pixel, placing a high level of demand on the texture buffer. Thus, poor performance of the texture buffer is capable of affecting a cascading degradation through the graphics system, stalling the render pipeline, and increasing the render or refresh times of displayed images.
Therefore, the design of memory systems and memory management plays a significant role in the implementation of new generation graphics systems. In some cases, Dynamic Random Access Memory (DRAM) or Synchronous DRAM (SDRAM) devices may be used to implement a texture buffer as they are generally less expensive and occupy less real estate than Static Random Access Memory (SRAM) alternatives. However, factors inherent in DRAM devices, and bus protocols, such as pre-charge time, activation time, refresh period, and others may complicate integration into high bandwidth applications such as high performance graphics systems. One example of a DRAM system that may be used in new generation graphics systems is a Double Data Rate SDRAM (DDR SDRAM) system. DDR SDRAM systems increase the throughput of DRAM memories, but they have not overcome all of the performance hurdles mentioned above.
FIG. 1 illustrates a common implementation of a DDR SDRAM system comprising a DDR SDRAM Controller coupled to a DDR SDRAM unit through an interface unit (Memory I/O). The Memory I/O is coupled to the DDR SDRAM unit through a set of pad circuits. In a DDR SDRAM, read-data is accompanied by a corresponding trigger signal, commonly referred to as a DQS signal. The DQS signal is commonly used by a host system, which may include an Application Specific Integrated Circuit (ASIC) coupled to the DDR SDRAM through an interface unit such as the Memory I/O, to sample and latch the read-data
Economically, the use of DRAM devices, such as DDR SDRAM, in graphics systems is still desirable, and possible if the above-mentioned performance limiting factors can be mitigated through consideration of certain characteristics unique to graphics systems, such as memory bandwidth having a higher priority than memory latency. For these reasons, a system and method for optimizing the utilization of DRAM memory subsystems, more particularly DDR SDRAM systems, as employed in graphics systems is desired.